COSC 201

Computer Organization and Architecture

Spring 2017

 

 

Syllabus        Schedule        Moodle

 

 

 

Schedule

 

 

 

 

 

Week

Date

 

Reading

Materials

1

1/23

Welcome (Short Class)

*No Labs

 

 

 

1/25

Computer Architecture Intro: Make Computers Common

P&H: 1.1-1.5

HW 1

 

1/27

Evaluate Performance

P&H: 1.6-1.11

 

 

 

 

 

 

2

1/30

Speak the Language Part I: Assembly

Lab 1

P&H: 2.1-2.3

 

 

2/1

Speak the Language Part II: Binary and Instructions

Hw 1 Due

P&H: 2.4-2.5

HW 2

 

2/3

Speak the Language Part III: Logic and Making Decisions

Quiz 1

P&H: 2.6-2.7

 

 

 

 

 

 

3

2/6

Support Procedures

Lab 2

(Lab 1 Due)

P&H: 2.8

 

 

2/8

ASCII and Addressing, Core dump

Hw 2 Due

P&H: 2.9-2.10

 

HW 3

 

2/10

Multithreading

Quiz 2

P&H: 2.11

 

 

 

 

 

 

4

2/13

Translate and Start Programs

Lab 3

(Lab 2 Due)

P&H 2.12, 2.15

 

 

2/15

Put Everything Together,

Understand Arrays vs. Pointers

Hw 3 Due

P&H: 2.13-2.14

HW 4

 

2/17

Compare MIPS, RISC, and x86 Architectures

Quiz 3

P&H: 2.16-2.21

 

 

 

 

 

 

5

2/20

Basic Logic and Addition

Lab 4

(Lab 3 Due)

P&H: 3.1-3.2, A.1-A.2, A.3, skip A.4, A.5

 

 

2/22

Multiplication and Division

HW 4 Due

P&H: 3.3-3.4, A.7-A.8

HW 5

 

2/24

Floating Point

Quiz 4

P&H: 3.5

 

 

 

 

 

 

6

2/27

Subword Parallelism

Lab:  Review Period

(Lab 4 Due)

P&H: 3.6-3.10

 

 

3/1

Memory

HW 5 Due

P&H: A.9

HW 6

 

3/3

Exam

 

 

 

 

 

 

 

7

3/6

Building a Datapath

Lab 5

P&H: 4.1-4.3

 

 

3/8

Controlling the Datapath

HW 6 Due

P&H: 4.4

HW 7

 

3/10

Controlling the Datapath

Quiz 5

P&H: 4.4

 

 

 

 

 

 

8

3/13-3/17

Spring Break

 

 

 

 

 

 

 

9

3/20

Pipelining

Lab 6

(Lab 5 Due)

P&H: 4.5

 

 

3/22

Creating a Pipelined Datapath

HW 7 Due

P&H: 4.6

HW 8

 

3/24

Avoiding Data and Control Hazards

Quiz 6

P&H: 4.7-4.8

 

 

 

 

 

 

10

3/27

Handling Exceptions/Interrupts

Lab 7

(Lab 6 Due)

P&H: 4.9

 

 

3/29

Increasing ILP

HW 8 Due

P&H: 4.10-4.11

HW 9

 

3/31

Application: Matrix Multiply

Quiz 7

P&H: 4.12-4.15

 

 

 

 

 

 

11

4/3

Memory Heirarchy

Lab: Review Period

(Lab 7 Due)

P&H: 5.1Š5.2

 

 

4/5

Cache Basics

HW 9 Due

P&H: 5.3

 

 

4/7

Exam

 

 

 

 

 

 

 

12

4/10

Measure and Improve Cache Performance, Dependability

Lab 8

P&H: 5.4-5.5

 

 

4/12

Virtual Memory

HW 10 Due

P&H: 5.6-5.7

HW 10

 

4/14

Cache Control

Quiz 10

P&H: A.10, 5.8-5.9

 

 

 

 

 

 

13

4/17

Ensure Cache Coherence

Lab 9

(Lab 8 Due)

P&H: 5.10, 5.12

 

 

4/19

Case Studies

HW 10 Due

P&H: 5.13-5.14

HW 11

 

4/21

Caches and Matrix Multiply

Quiz 11

P&H: 5.15-5.17

 

 

 

 

 

 

14

4/24

Parallel Processing

Lab 10

(Lab 9 Due)

P&H: 6.1-6.3

 

 

4/26

Multithreading and Multicore

HW 11 Due

P&H: 6.4-6.6

HW 12

 

4/28

Organize Communication

Quiz 12

P&H: 6.7-6.8

 

 

 

 

 

 

15

5/1

Benchmarking

Lab 10 (contÕd)

P&H: 6.10-6.14

 

 

5/3

Special Topics

HW 12 Due

 

 

 

5/5

Special Topics

(Lab 10 Due)

 

 

 

 

 

 

 

16

5/9

Final Exam (3:00pm-5:00pm)