1. What are the five classical components of a computer?
2. How is the principle of abstraction used in the design of hardware and software?
3. Sketch the hierarchy of levels of abstraction of computer software and hardware from digital logic at the lowest level to high level languages at the highest level.
4. What is the role of an instruction set architecture in this hierarchy?
5. How is performance of a computer measured?
6. What are Clock rate, Cycles per instruction, instruction mix, and how do they determine execution time for a program?
7. What are mips and mflops and why are they deceptive as measures of performance?
8. What is a benchmark suite and what are the advantages and disadvantages of using a benchmark to measure performance?
9. What are the relationships between a high level language, assembly language, and machine language?
10. What are typical arithmetic and logical instructions in an assembly language?
11. What are the addressing modes for the MIPS architecture?
12. What are the control instructions for the MIPS architecture? For if … else and loop constructs? For subroutine calls?
13. What instructions access memory in the MIPS architecture?
14. How do RISC and CISC architectures typically differ?
15. What are the principles guiding the design of a RISC instruction set?
16. What are the layouts (bit fields) of MIPS instructions (R-type, I-type, J-type)?
17. What does it mean for the opcodes and addressing modes for an architecture to be orthogonal? How well does the MIPS architecture achieve this?
18. Translate an if … else construct into assembly language.
19. Translate a simple while loop into assembly language.
20. What are the steps for a subroutine call, before during and after execution of the subroutine code, in a MIPS assembly program?
21. Draw transistor circuits for the following logic gates: NOT, NOR, NAND, OR, AND k-way NOR, k-way NAND.
22. Draw the logic gate circuits for the following components: Multiplexor (2k input lines, k control lines, 1 output line carrying the signal from the selected input); decoder (k input lines, 2k output lines, the selected one carrying a 1, the others 0); comparator (two sets of k input lines, one output line carrying a 1 if all corresponding inputs were equal, otherwise 0).
23. What is a PLA?
24. What is disjunctive normal form for a logical expression?
25. Show how a logical expression can be represented by a truth table, then by disjunctive normal form, and how this can be implemented by a PLA.
26. What is a clock?
27. What is a D-latch? How can it be implemented with logic gates? What is the role of the clock?
28. What do "level-triggered" and "edge-triggered" mean?
29. What is a flip-flop?
30. How is a register built out of flip-flops?
31. What is a register file? What combinational circuits are used in a register file?
32. How are a clock signal, a register file, and combinational logic for arithmetic/logic combined to form a CPU? What needs to be added to these three components for a complete CPU?
33. How is a memory chip organized from a set of flip-flops, address lines in, and data lines in and out?
34. What is a "three-state buffer" and what is its role in a memory chip?
35. What is the difference between SRAM and DRAM? What are the advantages and disadvantages of each?
36. What is a finite state machine?
37. How can a PLA be used to implement a FSM?
For the next four questions, assume that we are using 4-bit two's-complement signed integers.
38. What is the range of values which can be represented by 4-bit two's-complement integers? List the two's complement representations for those values.
39. How can we find the two's-complement representation of -k if we are given the two's-complement representation of k?
40. How do we add in two's complement? Subtract?
41. How can we detect whether overflow has occurred in two's-complement addition or subtraction? Give an example.
42. Sketch the circuit for a one-bit full adder. (This has three one-bit inputs: the a bit, the b bit, the carry-in bit; and two one-bit outputs: the result bit and the carry-out bit.)
43. Sketch a diagram for a one-bit ALU which can do AND, OR, Addition, and Subtraction. What control line(s) are needed?
44. Describe how 32 one-bit ALUs can be connected to form a full 32-bit ALU. What modifications need to be made to accommodate the MIPS slt instruction?
45. What difficulty does the carry in a simple (ripple-carry) ALU raise? Describe an idea for overcoming that difficulty.
46. Describe an efficient method for multiplying two two's-complement integers. Sketch the components needed for a circuit to do this electronically.
46a. What is Booth's Algorithm for multiplication?
< Note: Skip Division.>
47. How is a single precision floating point number represented according to IEEE 754 specifications?
48. Convert a hexadecimal representation of a string of bits to the decimal number it represents according to IEEE 754, and vice versa. For example, convert 0xC1470000 to decimal and convert 12.6875 to the hex representation of its IEEE format.
49. Why do the IEEE format floating point representations use bias 127 (single precision) and bias 1023 (double precision) representations for the exponent?
50. Describe the algorithm for adding two floating point numbers. Sketch the circuit needed.
51. Describe the algorithm for multiplying two floating point numbers. Sketch the circuit needed.
52. Assume that you are given the circuit diagram for a single clock cycle cpu for the reduced MIPS instruction set (as on p. 307 in the text) Trace the lines which would be active for a given instruction. Indicate the paths followed by the signals which are active and how the control lines determine the flow and the read/write operations. You should be able to so this for an R-type instruction (such as add, and, slt), for a beq, for a j, for a lw and for an sw.
e.g. trace add $16, $16, $17
beq $17, $0, addr
lw $18, 4($16)
53. What is the limiting factor on how fast the single-clock-cycle cpu can run?
54. Describe how the control unit for the single-cycle cpu might be implemented. Use a diagram, if that is helpful.
55. What are some advantages of the multi-clock-cycle cpu over the single-cycle cpu?
56. List the five standard stages for executing an instruction in a mullti-cycle cpu.
57. Briefly describe what happens at each stage for a multi-cycle cpu for each type of instruction (R-type, beq, lw, sw, j). Use a diagram to illustrate (p. 323 in the text).
58. Describe how the control unit for a multi-cycle cpu might be implemented using an FSM. How does the FSM indicate the time needed for each instruction?