COSC 201, Fall, 1999

Exam 2 from 1998

1.(a)Write the four-bit (including sign bit) two's complement representation for the numbers -3 and -6.

(b)Show how to carry out the operation(-5) + (-6) in four-bit two's-complement notation.

(c)How can you tell whether an overflow occurs in a finite-precision two's-complement addition or subtraction?Did an overflow occur in the operation in part (b) ?

2.(a)Assume that the value -79.4375 is stored in a 32 bit register using IEEE 754 single precision floating point format.What would be the hexadecimal representation for the bit pattern in the register?

(b)Why does the IEEE 754 representation of floating point numbers use bias- 127 notation for the exponent for single precision and bias-1023 notation for double precision numbers?
3.(a)Represent a one-bit full adder with a box with a plus symbol, represent a multiplexor with an oval with MUX on it, and use the usual logical gates.Sketch the diagram for a single bit ALU which can do the following operations:AND, OR, Addition using input a and input b or Not b.Indicate all input lines and output lines, include the carry lines.

(b)Show how four one-bit ALUs as constructed in part (a) can be wired together to form a four-bit ALU which can do bit-wise AND, bit-wise OR, Addition and Subtraction.Indicate what control lines are needed and what they do.

(c)Explain how to add the needed lines and control so that the ALU described in part (b) can carry out the MIPS slt operation (for a four bit word).

4. (a)Sketch the circuit for doing a floating-point add.Use the floating point registers below for the top of your circuit and show a similar floating point register at the bottom for storing the result.(b) Explain how the floating-point add is carried out on your circuit.

sexponentsignificandsexponentsignificand



5. Use the attached diagram for a single clock cycle CPU (the diagram with the large control oval near the center).Specify how each of the control lines A-I is set for the following instruction (for F indicate what the ALU should do):

sub$rd, $rs, $rt

ABCDEFGHI

lw$rt, addr($rs)

ABCDEFGHI



6.Refer to the diagram for a multicycle CPU (the one with red and green letters).

(a)Sketch the finite state machine needed to control this multicycle CPU, including states to handle overflow and not-an-opcode exceptions.Give names to each of the states corresponding to the clock cycle which it represents (you need NOT list all the control lines settings for each state, see below).

(b)List the control lines setting for the three following clock cycles for this multicycle machine.

Instruction decode, register fetch, branch target compute

ABCDEFRWWRegPCWrite

R-type execute

ABCDEFRWWRegPCWrite

lw (load word) write-back

ABCDEFRWWRegPCWrite

(c)What additional registers must be added to this CPU in order to handle exceptions such as not-an-opcode or overflow?What is the purpose of each of these registers?

(d)State two advantages of a multicycle CPU over a single cycle CPU.
7.(a)What is an exception? Give examples.

(b)How is a program restarted in the correct state and at the correct instruction after an exception has been handled by system code?