Computer Organization

Lab: Cache Control

Learn the circuit needed to create a data cache and the control for that cache.
Complete the circuit for the data cache. Hand test the circuit..
Read chapter 5 in the text.
Files to Use
           Cache register file.circ
           MemoryWith Delay.circ
control fsm 2x.doc
What to Hand In
            completed control fsm2.doc
            completed singleCache.circ
            report on testing

The file singleCache.circ has a LogiSim circuit for a 32-line data cache, 11 bit addresses( 5 bit line address, 6 bit tag), 24 bit data, a valid and a dirty bit for each line. The input lines and control lines for controlling the cache are indicated.

The file control fsm2x.doc describes a finite state machine for controlling the cache where the control lines depend both on the input lines and the state of the machine (a Mealy Machine).

1. Complete the table for state transitions and control given in control fsm2x.doc and save it.

2. Create a circuit which implements the machine described in 1 and save it as cacheControl.circ.

3. Add this circuit to singleCache.circ to complete the cache.

4. Place some data in the memory unit.

5. Test the cache circuit manually. First load the inputs to the cache. Second toggle the clock. Load new inputs. Continue to toggle the clock until the new inputs are latched into the input register. Load new inputs. Continue. Check memory after write-backs to see if the correct data went into the memory. Write a short report on your test sequence and the result. Report any apparent errors in execution. Be sure your sequence of cache accesses tests the different situations that can occur -- you will probably need to use only a limited number of memory addresses, but be sure to include some inputs that indicate no cache access.