Computer Organization

Lab: Pipeline CPU

Purpose
Understanding the organization of a pipeline cpu.
Method
Complete the implementation of a pipeline CPU in LogiSim
Preparation
Read chapter 4 in the text.
Files to Use
 
arraySum.s, arraydata.mem, control.circ (completed in lab 7), MiscComponents.circ, pipelineRegisters-start.circ, PipelineCPU1-start.circ, CPUComponents.circ (completed in lab 7), fileSpecs.pdf, pipelineRegisterFileSpecs.pdf     completed control.circ
What to Hand In
Completed pipelineRegisters.circ, completed PipelineCPU.circ
 
 

 
1. You should first replace the incomplete CPUComponents.circ in the PipelineCPU1-start.circ file with the CPUComponents.circ file you completed for lab 7, as follows:
a. Delete all the CPU Components circuits from the PipelineCPU file.
          b. Under Project - unload libraries, select CPUComponents to unload.
c. Under Project - load libraries - logisim libraries, select your completed CPUComponents.circ file to load
          d. Reinsert the CPUComponents circuits into the PipelineCPU diagram, with appropriate labels.
          e. Save the adjusted PipelineCPU file as PipelineCPU1.circ

2. Complete the pipelineRegisters-start.circ file.

         a. See the pipelineRegisterFileSpecs.rtf file for the specifications.
         b. Using the completed pipeline registers as a model, build the required register modules, save the file as pipelineRegisters.circ.
         c. Unload the pipelineRegisters-start.circ file from PipelineCPU1.circ by deleting all the pipeline registers and using project-unload libraries.
         d. Load your completed pipeline register file using project-load libraries, and replace the previous pipeline registers.
         e. The EX/Mem registers (PipeReg3-) should be placed in the column created by the clock and reset vertical lines under the EX/Mem label.
         f. The Mem/WB registers (PipeReg4-) should be placed in the column created by the clock and reset vertical lines under the Mem/WB label.

3. Complete the PipelineCPU1.circ

        a. Insert the circuits for branch address and jump address computations, and connect. The multiplexors at the top right select PC+4, branch, or jump.
        b. Route the appropriate control and data lines through the pipeline registers and connect controls appropriately.
        c. The data and control lines that need to connect to the register file for the WB stage are easiest to route by taking them toward the bottom after the MemToReg multiplexor, back across the the left, just above the main clock and reset lines, and back up to the register file. Note, the register-write control is at the top of the register file module.

4. Test your completed PipelineCPU1.circ as follows.

       a. Modify the arraysum.s file by inserting the needed nop instructions to avoid data hazards and branch/jump hazards for this pipeline. (Hint: branch and jump each need 3 nops inserted before the next instruction.
       b. Create the arraysum.mem file as you did for lab 7. Load it into instruction memory and arraydata.mem into data memory. Run slowly, at 0.5 Hz if you enable clock ticks. The results in the data memory should be the same as for lab 7, with the program cycling on the final branch at the end.


Extra Credit

Modify the PipelineCPU1 circuit so that the branch and jump only have a delay of a single clock cycle, as described in the book. You should use the same branch and jump address modules before, but you can add a branch-control module that outputs 1 if a beq should be taken. This should involve a comparator for the appropriate register values. This logic should be placed in the ID stage.