COSC 201, Spring, 2018
Syllabus

The course description contains details about the topics of this course and the organization of the course, including grading.

This syllabus presents the weekly topics and assignments. The details of the syllabus and adjustments will be filled in as the course proceeds.

Text: Computer Organization & Design: The Hardware/Software Interface, ARM ed.,  Hennessy and Patterson.  

Office hours: M 12-1, 4-5, W 12:30-1 and by appointment

Links: (ebook link)   (ARMv8 reference card)   (Link to SUSE linux for Raspberry Pi) libguile file   libunistring

Course Schedule

date                topic                                   reading                                       assignment/quiz


Jan   22        Short class                     H&P, chapter 1, sections 1.1-1.11   Homework 1      
        24        Class but no labs
        26         Homework 1 due (email to instructor)


        29        Levels of Abstraction      H&P, chapter 2, 2.1-2.3 
                    Assembly code
        31       Twos-complement,           H&P, chapter 2, 2.4-2.5                 Homework 2
                    Instruction formats   
        31       Lab 1                                (instructions for setting up linux OS for Raspberry Pi)
Feb    2      Quiz 1 due -- on Ch 1 (on Moodle)


Feb    5       Loops and Procedures       H&P, chapter 2, 2.6-2.8 
          7       Arrays and Pointers           H&P, chapter 2, 2.9-2.10, 2.14           
                     Addressing formats                                                              
          7       Lab 2a
          9       Homework 2 due (email to instructor)       


         12      No Class -- class during Tuesday free period
Tues 13   12:00-1:15  Parallel synchronization       H&P, chapter 2, 2.11-2.12         
                   Translating and starting programs 
         14     Putting it all together          H&P, chapter 2, 2.12-2.14, 2.19-2.20  
                                                           code: SelSortMain.c, Swap.s, SelSort.s    
         14      Lab 2   
         16     Quiz 2 due on Ch 2 


         19      Combinational logic            H&P, appendix A, sections A1-A3
         21      Building an ALU                H&P, section A5 (skip A4)                     Homework 3
         21      Lab3       


         26     Clocks, latches, registers     H&P, sections A7-A9     LogiSim Mem Circuits                
                  Memory elements  
         28     Finite State Machines         H&P, sections A9-A10  (Optional: A11-A13)
                  Faster Addition                   H&P, section A6
         28     Lab 5                            LogiSim circuit simulator-PC               LogiSim circuit simulator-MacOSX      
Mar    2     Homework 3 due (email to instructor)          


          5       Multiplication                      H&P, Ch 3, sections 3.1-3.3 (skip 3.4) 
          7       Floating point arithmetic       H&P, 3.5-3.7, 3.9-3.11                  
          7       Lab 6     (due March 19)
          9       Quiz 3 (on appendix A) due


Mar   10 - 18       Spring Break


         19        No Class
         21         Exam                                   Sample Exam 
         21        No Lab               


         26      Single cycle CPU                 H&P, Ch. 4, 4.1-4.4   Homework 4
         28      Multi-cycle cpuPipeline CPU                      H&P, 4.5-4.6
         28      Lab 7 - part 1 
Apr     1      (Sunday)               Homework 4 due- not accepted late!  (email to instructor)                                                   


Apr     2      Pipeline CPU, Hazards, Data forwarding     H&P, 4.7-4.8 
           4      Branch Prediction, Exception Handling              H&P, 4.8-4.9 
           4       Lab 7 - part 2                                                       Controls for datapath             
           6      Quiz 4 due


            9     No Class -- make up on Tuesday Apr 17, 12:00 - 1:10  
          11     Instruction Level Parallelism  H&P 4.10-4.11, 4.14-4.15
          11     Lab 8 - pipeline cpu
          13     Quiz 5 due


          16      Memory hierarchy, cache   H&P, Ch 5, 5.1-5.4 (to pg 423)
Tues 17      12:00 - 1:10  Enhanced Cache Performance  H&P, Ch 5, 5.4 classwork   cache-diagrams
          18       Error-correcting memory         classworkSolution
                      Virtual Memory                H&P, Ch. 5, 5.5, 5.7-5.8 (skip 5.6)     
          18      Lab 9 - optimizing code for pipelines
          20       Quiz 6 due (5.1-5.5)


          23       Cache control,                   H&P, Ch 5, 5.9-5.10, 5.12 (pp11-17), 5.13-5.16
          25       Parallel Computing             H&P, Ch 6, 6.1-6.5
                     Multithreading         
          25       Lab 10  (Due May 2)
          27        Quiz 7 due  (5.7-5.10)  


          30      No Class
May     2       Different Approaches   Review                       Sample Final Exam            Last day to hand in labs!


       Final Exam: Thursday, May 10, 9:00-11:00