COSC 201, Fall, 2017
Syllabus

The course description contains details about the topics of this course and the organization of the course, including grading.

This syllabus presents the weekly topics and assignments. The details of the syllabus and adjustments will be filled in as the course proceeds.

Text: Computer Organization & Design: The Hardware/Software Interface, ARM ed.,  Hennessy and Patterson.  (ebook link)   (ARMv8 reference card)

Office hours: M 12-1 and W 4-5, and by appointment

Course Schedul

date                topic                                   reading                                       assignment/quiz


Aug   29        Short class                     H&P, chapter 1, sections 1.1-1.11   Homework 1       
        30        Levels of Abstraction      H&P, chapter 2, 2.1-2.3 
                    Assembly code


Sept     4      Twos-complement,           H&P, chapter 2, 2.4-2.5                 Homework 2
                     Instruction formats   
          4/6      Lab 1           
            6       Loops and Procedures       H&P, chapter 2, 2.6-2.8                                                                     
            8       Homework 1 due (email to instructor)                                   Quiz 1 due -- on Ch 1 (on Moodle)


          11       Arraysand Pointers           H&P, chapter 2, 2.9-2.10, 2.14           
                     Addressing formats        
          11/3     Lab 2    
          13       Parallel synchronization       H&P, chapter 2, 2.11-2.12         
                     Translating and starting programs
          15       Homework 2 due (email to instructor) 

         18       Putting it all together          H&P, chapter 2, 2.12-2.14, 2.19-2.20  
                                                           code: SelSortMain.cpp, Swap.s, SelSort.s
         18/20      Lab3 
         20       Combinational logic            H&P, appendix A, sections A1-A3
         22      Quiz 2 due on Ch 2


         25       Building an ALU                H&P, section A5 (skip A4)                     Homework 3   
         25/27   Lab 5                            LogiSim circuit simulator-PC               LogiSim circuit simulator-MacOSX      
         27       Clocks, latches, registers     H&P, sections A7-A9     LogiSim Mem Circuits                
                     Memory elements         


Oct     2       Finite State Machines         H&P, sections A9-A10  (Optional: A11-A13)
                    Faster Addition                   H&P, section A6
           2/4     Lab 6
           4      Multiplication                      H&P, Ch 3, sections 3.1-3.3 (skip 3.4)
           6     Homework 3 due (email to instructor)    


Oct     9      Fall Break -- no class on Monday, no lab this week
          11     No Class   
          13    Quiz 3 (on appendix A) due  -- Lab 6 Due

         16       Floating point arithmetic       H&P, 3.5-3.7, 3.9-3.11 
        16/18 No Lab               
         18       Exam                                   Sample Exam 


         23      Single cycle CPU                 H&P, Ch. 4, 4.1-4.4    Single-cycle pdf format    Homework 4
         23/25  Lab 7 - part 1 
         25      Multi-cycle cpuPipeline CPU                      H&P, 4.5-4.6  
         29 (Sunday)               Homework 4 due- not accepted late!  (email to instructor)                                                   


         30      Pipeline CPU, Hazards, Data forwarding     H&P, 4.7-4.8              
         30/1     Lab 7 - part 2                                                       Controls for datapath
  Tuesday, Oct 31 Class: 12:00 - 1:10 Instruction Level Parallelism  H&P 4.10-4.11, 4.14-4.15

Nov    1         No Class   / Labs will meet
           3      Quiz 4 due


            6     No class - lab will meet to complete lab7 or start on lab 8
            8    Lab 8 - pipeline cpu     (Due Nov 29)
            8     Memory hierarchy, cache   H&P, Ch 5, 5.1-5.4                        Class and labs will meet!!
                   Enhanced Cache Performance   classwork   cache-diagrams     
           10     Quiz 5 due


           13        Error-correcting memory         classworkSolution
                      Virtual Memory                H&P, Ch. 5, 5.5, 5.7-5.8 (skip 5.6) 
           13        Lab 8 - pipeline cpu        (Due Nov 29)
           15       No class, labs will meet for additional time on lab 8


        18-26         Thanksgiving Break


          27            No Class/ Lab will meet
          27/29      Lab 9 - optimizing code for pipelines
          29        Cache control,                   H&P, Ch 5, 5.9-5.10, 5.12 (pp11-17), 5.13-5.16
Thursday Nov 30, 1-4:   extra office hours for lab 9
Dec    1         Quiz 6 due (5.1-5.5)


            4          Parallel Computing             H&P, Ch 6, 6.1-6.3
                        Shared Memory and Message-Passing 
            4/6       Lab 10 (Due Dec 13)
            6         Multithreading, SMP          H&P, Ch 6, 6.4-6.5
            8          Quiz 7 due  (5.7-5.10)  


           11         Different Approache
           11/13     No new lab -- labs will meet for an hour if you need it: 4-5, MW and 12:20-1:15 W (instead of 11:20)
           13         Review                       Sample Final Exam            Last day to hand in labs!


       Final Exam: TBA