COSC 201, Fall, 2016
Syllabus

The course description contains details about the topics of this course and the organization of the course, including grading.

This syllabus presents the weekly topics and assignments. The details of the syllabus and adjustments will be filled in as the course proceeds.

Text: Computer Organization & Design: The Hardware/Software Interface, 5th ed.,  Hennessy and Patterson.  

Office hours: 12-1, MW and by appointment

Course Schedule

date                topic                                   reading                                       assignment/quiz


Aug   25        Short class                     H&P, chapter 1, sections 1.1-1.11   Homework 1          


         29       Levels of Abstraction      H&P, chapter 2, 2.1-2.3                 MARS Simulator
                   Assembly code    
         29/31      Lab 1           
         31      Twos-complement,           H&P, chapter 2, 2.4-2.5                 Homework 2
                   Instruction formats                                                                    
Sept    2       Homework 1 due (email to instructor)       Quiz 1 due (on Moodle)


           5      Loops and Procedures       H&P, chapter 2, 2.6-2.8              
                 
           5/7      Lab 2    
           7      Arraysand Pointers           H&P, chapter 2, 2.9-2.10, 2.14           
                   Addressing formats  
           9       Homework 2 due (email to instructor) 

         12       Parallel synchronization       H&P, chapter 2, 2.11-2.12         
                    Translating and starting programs
         12/14      Lab3 
         14      Putting it all together          H&P, chapter 2, 2.12-2.14, 2.16-2.19  
                                                           code: SelSortMain.s, Swap.s, SelSort.s
         16      Quiz 2 due


         19      Combinational logic            H&P, appendix B, sections B1-B3        Combinational logic-pdf-format
         19/21      Lab 4
         21      Building an ALU                H&P, section B5 (skip B4)                     Homework 3    
                             


         26     Faster Addition                   H&P, section B6
         26/28      Lab 5                                                                                                              LogiSim circuit simulator-PC
         28      Clocks, latches, registers     H&P, sections B7-B8     LogiSim Mem Circuits          LogiSim circuit simulator-MacOSX
         30     Homework 3 due (email to instructor)    


Oct     3      Memory elements &            H&P, sections B9-B10                   
                   Finite State Machines          (Optional: B11-B12)
           3/5      Lab 6 
           5      Multiplication                      H&P, Ch 3, sections 3.1-3.3 (skip 3.4) Multiplication in pdf
           7    Quiz 3 (on appendix B) due  

         10     Fall Break -- no class on Monday, no lab this week           
         12     Floating point arithmetic       H&P, 3.5-3.7, 3.9-3.10     


         17    Exam                                   Sample Exam 
         17/19    No Lab, Lab 6 due
         19    Single cycle CPU                 H&P, Ch. 4, 4.1-4.4    Single-cycle pdf format    Homework 4
         21    Quiz 4 due                                                             


         24     Multi-cycle cpuPipeline CPU                      H&P, 4.5-4.6              pipeline in pdf               
         24/26     Lab 7 - part 1
         26     Pipeline CPU, Hazards, Data forwarding     H&P, 4.7-4.8            Data forwarding in pdf
         28     Homework 4 due  (email to instructor)


          31     Exception Handling              H&P, 4.9                   Exception Handling in pdf
31/Nov 2     Lab 7 - part 2                                                       Controls for datapath
Nov     2     Instruction Level Parallelism  H&P 4.10-4.11, 4.14-4.15
            4     Quiz 5 due


            7     Memory hierarchy, cache   H&P, Ch 5, 5.1-5.4       
            7/9     Lab 8 - pipeline cpu
            9     Enhanced Cache Performance  H&P, Ch 5, 5.4-5.5 classwork   cache-diagrams
          11      Quiz 6 due (5.1-5.5)


          14      Error-correcting memory         classworkSolution
                    Virtual Memory                H&P, Ch. 5, 5.7-5.8 (skip 5.6)
          14/16      Lab 9 - optimizing code for pipelines (due Dec 1)
          16      Cache control,                   H&P, Ch 5, 5.9-5.10, 5.12 (pp11-17), 5.13-5.16
          18      Quiz 7 due  (5.7-5.10)


        19-27         Thanksgiving Break


          28        No Class
          28/30        Lab as scheduled       Lab 10 (Due Dec 7)
          30       Parallel Computing             H&P, Ch 6, 6.1-6.3
                     Shared Memory and Message-Passing 
Dec      1  (Thurs)      office hours 1:00-3:00 to discuss lab 10 or any other issues


           5       Multithreading, SMP          H&P, Ch 6, 6.4-6.5   
           5/7       Lab 10
           7       Different Approaches                           Sample Final Exam            Last day to hand in labs!


       Final Exam: Wednesday, Dec 14, 1-3. 314 McGregory.