# COSC 201: Computer Organization

## Homework 3: Logic Circuits

1. Design a transistor circuit to implement an XOR gate: if both inputs are the same, then 0 is output, if they are different, then 1 is output. Use as few transistors as possible. (One way to start is to use the logic that (A XOR B) = (A OR B) AND Not(A AND B). This may or may not be helpful.)

Note: it is tricky to use transistors in LogiSim. If you want to do this, I have shown the circuit for a nor-gate. Note: 1. Use N- type transistors. 2. Arrow in transistor should point away from ground. 3. Power should be a pull-resistor with a value of 1 set.

2(a). Consider a circuit that has two single bit data inputs, A and B, and two single bit data outputs, C and D. The circuit has a single bit control line, S and works as follows:

If S = 0, then C = A and D = B.

If S = 1, then C = B and D = A.

Draw a logic circuit using the basic gates that implements this switch.

2(b) Consider the following network (called a butterfly network), where the Ai represent incoming data and the Bi the outgoing data. Assume that each switch works as specified in part (a). Assume that each switch has a separate control line and that these control lines are specified **r.c** where **r** is the row (numbered 0 to 3 from the top) and **c** is the column (numbered 0 to 2, left to right).

Give switch settings that would route A0 to B5, leaving unspecified any switches that are not needed.

Give switch settings that would route A6 to B0.

Can every input be connected to every output?

Give routings for two A inputs to two B outputs that are incompatible (cannot be satisfied at the same time).

3. Consider the addition of two two-bit numbers (no carry-in). This would have four inputs and three outputs (the two-bit result and a carry-out bit).

(a) Write out the 16-line truth table. (four columns for input, three for output).

(b) Sketch the PLA circuit (using the lines and dot notation).

(c) How many AND-lines (vertical) would be needed for 64-bit addition, including carry-in and carry-out bits. Could this be done on a PLA?