Computer Organization

Lab: Pipeline CPU

Purpose
Understanding the organization of a pipeline cpu.
Method
Complete the implementation of a pipeline CPU in LogiSim
Preparation
Read chapter 4 in the text.               working versions of control.circ and CPUComponents.circ
Files to Use
 
 test.s, test.mem, testdata.memarraySum.s, arraySum.mem, arraydata.mem, control.circ (completed in lab 7), MiscComponents.circ, CPUComponents.circ (completed in lab 7), pipelineRegisters-start.circ, PipelineARM-CPU1-start.circ, fileSpecs.pdf, fileSpecs.docx, pipelineRegisterFileSpecs.docx,  pipelineRegisterFileSpecs.pdf
What to Hand In
Completed pipelineRegisters.circ, completed PipelineCPU.circ
 
 

 
1. You should first copy your completed CPUComponents.circ and control.circ files from lab 7 into the folder for this lab. Then when you open
PipelineARM-CPU1-start.circ the components should be correct in your circuit or available from the menu. (If you have not completed either of these files from lab 7, see the instructor.)
 

2. Complete the pipelineRegisters-start.circ file.

         a. See the pipelineRegisterFileSpecs.docx (pdf) file for the specifications.
         b. Using the completed pipeline registers as a model, build the required register modules, save the file as pipelineRegisters.circ.
         c. Unload the pipelineRegisters-start.circ file from PipelineCPU1.circ by deleting all the pipeline registers and using project-unload libraries.
         d. Load your completed pipeline register file using project-load libraries, and replace the previous pipeline registers.
         e. The EX/Mem registers (PipeReg3-) should be placed in the column created by the clock and reset vertical lines under the EX/Mem label.
         f. The Mem/WB registers (PipeReg4-) should be placed in the column created by the clock and reset vertical lines under the Mem/WB label.

3. Complete the PipelineCPU1.circ

        a. Insert the circuits for branch address and control computations, and connect. The multiplexors at the top right select PC+4 or branch.
        b. Route the appropriate control and data lines through the pipeline registers and connect controls appropriately.
        c. The data and control lines that need to connect to the register file for the WB stage are easiest to route by taking them toward the bottom after the MemToReg multiplexor, back across the the left, just above the main clock and reset lines, and back up to the register file. Note, the register-write control is at the top of the register file module.

4. Test your completed PipelineCPU1.circ as follows.

       a. Modify the arraysum.s file by inserting the needed nop instructions to avoid data hazards and branch hazards for this pipeline. (Hint: branch needs 3 nops inserted before the next instruction.) Then modify the arraysum.mem file by inserting 00000000 for each nop in the arraysum.s file. Rename this arraysum-nops.mem.
       b. Use the arraysum-nops.mem file as you used arraysum.mem for lab 7. Load it into instruction memory and arraydata.mem into data memory. Run slowly, at 0.5 Hz if you enable clock ticks. The results in the data memory should be the same as for lab 7, with the program cycling on the final branch at the end.
       c. You can also test using the test.mem and testdata.mem files by inserting the needed nops into test.mem.


Extra Credit

Modify the PipelineCPU1 circuit so that the branches have a delay of a single clock cycle, as described in the book. You should use the same branch address module as before. You should modify the branch control circuit in CPUComponents.circ to include the test for zero (see MiscComponents). This logic should be placed in the ID stage with the multiplexor selecting branch or PC+4. When a branch is selected, zeroes should be sent to the IR instead of the instruction from memory.

To test, use arraysum-nops.mem modified to eliminate the nops inserted for the branches.